Specification and Design of a New Memory Fault Simulator

This paper presents a new Fault Simulator architecture for RAM memories. The key features of the proposed tool are: 1) user-definable fault models, test algorithm, and memory architecture; 2) very fast simulation algorithm; 3) ability to compute the coverage of any provided test sequence w.r.t. a user-defined set of fault models, and to eliminate redundant operations; 4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints.